button. This process is easily automated and works great.
The physical interface consists of 4 signals, a clock signal, data in signal, data out signal, and mode select signal. Using these 4 signals it is possible to read and write information to the special JTAG silicone present in the target under test. How you may ask? Well first let's draw a block diagram of the JTAG registers in silicone.
You see on the left are the 4 signals, 3 in and 1 out. Synchronous serial is how the data is transmitted on these wires. Take a sample 8 bit hex number of 0x5A, which in binary is b01011010. To write this value across a synchronous serial port you need to take each bit of the number one at a time and assert it on the data in signal. When the data in signal represents your bit you need to toggle the clock signal from low to high. (see note 2) Look at this diagram of the signals:
You see that the data transitions on the falling edge of the clock so that it's stable by the rising edge of the clock. Each bit of the number is transmitted one at a time using the clock signal to mark when each bit is valid. The neat thing about synchronous serial is that its only perspective of time is the clock signal. You could start sending the byte of data and stop on the 3rd bit for 60 years and come back and finish with no problems.
Keep in mind when you are implementing something JTAG you are the MASTER! The sync serial connection is a bus in computer terms. With every bus in a computer someone has to be the master and everyone else is a slave. Since we are the master it is OUR responsibility to make ALL the signals perform as described except the data out which is how the target talks back to us.
Now you understand the basic principles of synchronous serial lets talk about data in and data out. Some designs share data in and out on the same signal (such as PS2 keyboards and mice which are nothing more than synchronous serial devices) and others separate the data. JTAG separates the data lines and we'll discuss why later on. However, you can take the above images and add an additional data line and realize that one is data in and one is data out. The difference is we write data in, the JTAG hardware writes data out. We have to sample the data out on the correct phase of the clock to reconstruct information the JTAG module is sending back to us.
Looking back at the JTAG registers diagram you'll see that the signals go into the JTAG interface silicone and then there are 2 registers on the other side called instruction and data. Physically through JTAG we only ever write to these two registers. When we clock data in it always goes to one or the other. How do we select which one we want? The mode select signal of course! It's not just as simple as setting the mode select to 1 for this register and 0 for that register. I wish it were! The JTAG interface is a complex hardware state machine (which is beyond the scope of this document). The JTAG interface has several states that accomplish reading and writing to these registers. Depending on what state the JTAG interface is in; the mode select signal has different effects.
Lets talk about the JTAG interface state machine. The diagram below shows the state machine. Each state represents a single clock cycle, the numbers as the state transitions (on the lines) represent the state of the mode select signal, and the data in signal is not really displayed. Remember it's the clock and mode select signals that control the states.
The image is slightly fuzzy because I stole it from a pdf. I don't feel like re-creating it. This state machine took me about a day to figure out originally because my printer left off about half of it and I didn't know. You are lucky enough to have the complete state machine before you. This machine shows the relationship of the clock signal and mode select signal.
Lets say for example we are in the Run-Test/Idle state and wish to get to Test-Logic-Reset.
You would need to set mode select high and cycle the clock once. This will put you in the
Select-DR-Scan state. If you leave the mode select high and cycle the clock again you will be
in the Select-IR-State, and with one more clock cycle you'll be in the Test-Logic-Reset state.
If we were for example in the Run-Test/Idle state and wanted to get into the Capture-DR state we
would set mode select high for one clock cycle, then set it low for the next clock cycle. We
would now be in the Capture-DR state. You may need to study the flowchart for a minute before
you understand what I'm saying.
O.K. now that you understand what I'm saying we need to figure out how to do something with it.
Remember the JTAG register diagram at the top shows that there are only 2 registers accessible
on the other side of the JTAG interface state machine. The two paths in the flowchart that
start with the states Select-DR-Scan and Select-IR-Scan are how you access those two registers.
DR is the data register and IR is the instruction register. lets first talk about getting data
in and out of either of these registers and then talk about what happens next.
Let's use the data register for our examples, the instruction register would be exactly the same
only starting at a different state. Lets start with the 32 bit data register. Both registers
in the JTAG core are nothing but shift registers that you send bits into LSB to MSB. To put
bits into the registers you must get into the Shift-DR state. While in the Shift-DR state AND
mode select is low each clock cycle will sample the data-in and shift it into the LSB of the
data register. Remember the sync serial talks above, you use that method at this time to send
each bit of your data into this register. To exit this state you must set mode select high. One
thing to remember is that on exit a bit will be sampled into your register so you must set mode
select high on your last bit. Now you must execute states all the way through the Update-DR
state using the clock and mode select. The value of the data line doesn't matter except when
in the Shift-DR state.
Writing to the instruction register is identical except its only 5 bits wide so make sure you
don't send to many bits. Remember this is a hardware state machine, it does not have any idea
how many bits you have clock into it. It will sit there forever shifting in bits until you
set the mode select signal.
Well now we see how to write to the 2 registers but how do we read? That's why JTAG uses a
separate data-in and data-out. A write IS a read and a READ is a WRITE! As you clock in each
bit in the Shift-DR state the register is also being clocked out the data-out signal. The data
you see coming out is the contents of the register before you modified it. This makes a strange
situation in that you cannot just read a register you have to write it as well. So you must
always conjure up a valid write value for the register you are reading otherwise you will have
problems. However, its not necessary to do anything with the data being clocked out when you are
writing, but you could if you wanted to!
Now you know how to navigate states within the JTAG interface machine and should be able to
employ that to modify the two registers instruction and data. Before we go on with what to do
with them, lets talk about initial states in the JTAG interface machine. When your JTAG tool
first attaches to the target you really don't know for sure what state the JTAG interface machine
is in. What you need to do is get it into a known state which is Test-Logic-Reset. To get
there from any state what you need to do is set mode select high and run the clock through at
least 5 times. You can pick ANY state in the machine and count 5 cycles of mode select = 1 and
you will find yourself in the Test-Logic-Reset state. Then you need 1 cycle with the mode select
low and your in Run-Test/Idle which is the best place to leave the machine when your not working
with it.
O.K. almost done now. What to do with the instruction and data registers? Simple, see the
registers to the far right in the JTAG register diagram labeled Sample Register A..? Those
registers are the heart of your JTAG system. You write into the instruction register which
register you want to read/write. Then when you read/write the data register you are actually
read/writing the selected register on the right. What values do you use in the instruction
register, well that depends on your JTAG target. That's why I didn't name the registers on the
right. They can be different for each type of target. You need to read about your targets JTAG
interface at this point and find out what registers you have on the right and what values you
write to the instruction register to get at them.
Now you know how to read and write to the control registers in a JTAG system. You can do a lot
of neato things with JTAG including emulation which is the focus of these documents. Its not
in the scope of this document to cover hardware validation or flash programming. If you want
to learn more about emulation via JTAG then read on to the next tutorial.
Here we will stop with JTAG and in the next section we will discuss the registers on the right
and how to use them to emulate a processor (specifically the AU1500 by Alchemy Semiconductor).
The next section will assume that you know how to write to the registers on the right and not
dedicate any time to JTAG. The lesson is, JTAG is just a way to communicate to special function
registers inside your target. Those registers can and will be different from target to target.
Note 1) Bed-of-nails testing refers to a method of test where on the production floor was a custom jig that could hold a board under test. The jig had points that looked like nails sticking up that would contact strategically located test points on the board in test when it was placed in the jig. Then some diagnostic software or perhaps the nails themselves would invoke activity on the board that would ensure everything was functional. This is very labor intense and could damage hardware form the points of nails!
Note 2) The signaling described assumes that the synchronous serial port clocks its data on the rising edge of the clock. This can and will be different in almost all designs and it's important that you find out the requirements of your design. JTAG clocks on the rising edge of the clock as described above. It is also important to know if you start sending the MSB or LSB first which in JTAG its LSB.
